Strategies for Optimization of Time Delay in Nanoelectronics Circuits with Process Variations Effects

Juan Tisza, Mario Chauca

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

In this work it is presented and evaluated two strategies to achieve the optimization of the variance of delay in nanoelectronic digital circuits, taking into account the variations due to the manufacturing process. The evaluations of both strategies are developed through applications in 8 ISCAS circuits. The results show comparisons in percentage changes in the variances of delay time and power consumption on each circuit because of applying these two strategies. In this article, the results are presented in full form for all tested circuits. One of the strategies is called ONE TRACK and the other TRACKING. The first uses the LaGrange method with Karush Kuhn Tucker's theorem and the second develops a progressive resizing, increasing the width of the critical gates in discrete steps of constant value as far as restrictions allow. During the application of the procedure, the total state of the circuit is evaluated in each step. In both strategies, the variance of the delay time is optimized with restriction of the area used and the power consumed is calculated. The results are presented in tabular and graphical form. Finally, conclusions and observations from the study are issued. The codes are implemented in C++ and it is used a 65 nm technology.

Original languageEnglish
Title of host publicationSHIRCON 2019 - 2019 IEEE Sciences and Humanities International Research Conference
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781728138183
DOIs
StatePublished - Nov 2019
Externally publishedYes
Event2019 IEEE Sciences and Humanities International Research Conference, SHIRCON 2019 - Lima, Peru
Duration: 13 Nov 201915 Nov 2019

Publication series

NameSHIRCON 2019 - 2019 IEEE Sciences and Humanities International Research Conference

Conference

Conference2019 IEEE Sciences and Humanities International Research Conference, SHIRCON 2019
CountryPeru
CityLima
Period13/11/1915/11/19

Keywords

  • Consumed Power
  • Delay
  • Lagrange Method
  • Optimization
  • Resizing
  • Static statistical of time analysis (SSTA)

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